This invention relates to phase-locked loop circuits. More particularly, the invention relates to a digital phase-locked loop circuit for locking an output frequency both as to its frequency and its phase to an input frequency signal.
Phase-locked loop circuits have found wide application in the prior art. Control systems, navigation systems, radar, telemetry tracking and communications receivers and bit synchronizers all employ various forms of phase-locked loops to improve performance and enhance capability. Modern electronic technology (e.g. microprocessors and large-scale-integrated-circuits (LSI)) have enabled more exotic embodiments of this basic electronic circuit, including digital approaches. However, digital embodiments of phase-locked loops, such as that disclosed in U.S. Pat. No. 3,736,590, suffer from several disadvantages. Even with the use of LSI circuits, the basic circuit is quite complex, requiring a large number of components to implement the phase-locked loop functions, i.e., loop filter, voltage-to-frequency conversion, phase detection, etc. Accordingly, circuit susceptibility to temperature drifts, circuit reliability, cost to manufacture, and other problems result.
As disclosed in U.S. Pat. No. 3,736,590, the voltage-to-frequency function of the phase locked loop is accomplished through the use of a programmable divider circuit where the desired output frequency is programmed from a microprocessor. The output frequency is then phase shifted to obtain the phase-locked output frequency signal. This phase shift function also must be programmed from the microprocessor. Where a fine resolution in both frequency generation and phase shifting is required, the programmable divider approach simply is not adequate. The resolution of the programmable divider approach is controlled by the time interval of one clock cycle of the clocking signal to the programmable divider. One bit of the programming code being equivalent to one clock cycle time resolution between output pulses of the programmable divider. Applications requiring a higher degree of resolution in the frequency and phase lock of the output frequency signal for the same number of programming bits from the microprocessor require finer control of the voltage-to-frequency function than can be achieved through the use of a programmable divider. Additionally, the phase shift function requires several circuit components which suffer from the aforesaid disadvantages, and adds to the phase locking instability of the loop due to short term phase shift jitter.
Because of the limitations present in the prior art, it would be advantageous to provide a digital phase locked loop circuit which provides a high degree of phase and frequency resolution to accurately phase lock the output to the input. It would also be advantageous to eliminate the need for a discrete component implementation of the phase shift function thereby to remove a large number of components required to implement the phase locked loop circuit and to remove the phase inaccuracies due therefrom.